11 June, 2019
Job ID: 2019061102
Job Role: VTL Design and Verification Engineer SMTS
Eligibility: (BE/BTech/ME/MTech/MS) from any of the premier engineering institutes.
Experience: 2-6 Years
Vacancies: Not Mentioned
Salary: Not Mentioned
Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesizable design using Verilog/System Verilog.
Primary Technical skills:
1. Hands on experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification.
2. Good understanding of IP Verification Methodologies, Verification procedures and practices are plus
3. Verilog / System Verilog / System C
4. RTL in developed for FPGAs/ASICs/IPs
5. He/ She must be able to create verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes.
6. He/ She would need to engage with customers for Deployment and R&D assistance.
7. Exposure of object oriented programming using languages such as C++ is advantage
8. Experience in scripting languages such as Perl, Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc